{
// Place your snippets for verilog here. Each snippet is defined under a snippet name and has a prefix, body and
// description. The prefix is what is used to trigger the snippet and the body will be expanded and inserted. Possible variables are:
// $1, $2 for tab stops, $0 for the final cursor position, and ${1:label}, ${2:another} for placeholders. Placeholders with the
// same ids are connected.
// Example:
// "Print to console": {
// "prefix": "log",
// "body": [
// "console.log('$1');",
// "$2"
// ],
// "description": "Log output to console"
// }
//时序逻辑
"shixu template": {
"prefix": "Shixu",
"body": [
"always_ff@(posedge clk or negedge rst_n)begin",
" if(!rst_n)begin",
"",
" end",
" else if() begin",
"",
" end",
"end",
]
},
//计数器
"jsq template": {
"prefix": "jsq",
"body":[
"reg var;",
"always_ff @(posedge clk or negedge rst_n)begin",
" if(!rst_n)begin",
" var <= 0;",
" end",
" else if(add_var)begin",
" if(end_var)",
" var <= 0;",
" else",
" var <= var + 1;",
" end",
"end",
"assign add_var = 1;",
"assign end_var = add_var && var == x-1 ;",
]
},
//组合逻辑
"zuhe template": {
"prefix": "zuhe",
"body": [
"always_comb begin",
"${1};",
"end"
]
},
//仿真
"test template": {
"prefix": "Test",
"body": [
"`timescale 1ns/1ns",
"",
"module ${1:testbench_name}();",
"",
"reg clk;",
"reg rst_n;",
"",
"//uut的输入信号",
"reg[3:0] din0;",
"reg din1;",
"",
"//uut的输出信号",
"wire dout0;",
"wire[4:0] dou1;",
"",
"//时钟周期，单位ns，在这里修改时钟周期",
"parameter CYCLE = 20;",
"",
"//复位时间，此时表示复位3个时钟周期的时间",
"parameter RST_TIME = 3;",
"",
"//待测试模块例化",
"module_name uut(",
" .clk (clk ),",
" .rst_n (rst_n ),",
" .din0 (din0 ),",
" .din1 (din1 ),",
" .dout0 (dout0 ),",
" .dout1 (dout1 )",
");",
"//生成本地时钟50M",
"initial begin",
" clk = 0;",
" forever",
" #(CYCLE/2)",
" clk=~clk;",
"end",
"",
"//产生复位信号",
"initial begin",
" rst_n = 1;",
" #2;",
" rst_n = 0;",
" #(CYCLE * RST_TIME);",
" rst_n = 1;",
"end",
"",
"//输入信号din0赋值方式",
"initial begin",
" #1;",
" //赋初值",
" din0 = 0;",
" #(10*CYCLE);",
" //开始赋值",
"",
"end",
"",
"//输入信号din1赋值方式",
"initial begin",
" #1;",
" //赋初值",
" din1 = 0;",
" #(10*CYCLE);",
" //开始赋值",
"",
"end",
"",
"endmodule",
]
},
//通用状态机
"ztj template": {
"prefix": "Ztj",
"body": [
"always_ff@(posedge clk or negedge rst_n)begin ",
" if(!rst_n)begin ",
" state_c <= IDLE;",
" end ",
" else begin",
" state_c <= state_n; ",
" end",
"end",
"",
"",
"always_comb begin ",
"unique case(state_c) ",
" IDLE: begin ",
" if(idl2s1_start)begin ",
" state_n = S1;",
" end",
" else begin",
" state_n = state_c; ",
" end",
" end",
"",
" S1:begin",
" if(s12s2_start)begin",
" state_n = S2;",
" end",
" else begin",
" state_n = state_c;",
" end",
" end",
" S2:begin",
" if(s22s3_start)begin ",
" state_n = S3;",
" end",
" else begin",
" state_n = state_c;",
" end",
" end",
" default:begin",
" state_n = IDLE;",
" end ",
" endcase",
"end",
"//第三段：设计转移条件",
"assign idl2s1_start = state_c == IDLE && ;",
"assign s12s2_start = state_c == S1 && ;",
"assign s22s3_start = state_c == S2 && ;",
" ",
" //第四段：同步时序always模块，格式化描述寄存器输出（可有多个输出）",
"always_ff@(posedge clk or negedge rst_n)begin",
" if(!rst_n)begin",
" out1 <=1'b0 //初始化",
" end",
" else if(state_c==S1)begin",
" out1 <= 1'b1;",
" end",
" else begin",
" out1 <= 1'b0;",
" end",
"end",
]
},
"Jsq3 template": {
"prefix": "Jsq3",
"body": [
" always_ff@(posedge clk or negedge rst_n)begin",
" if(!rst_n)begin",
" cnt0 <= 0;",
" end",
" else if(add_cnt0)begin",
" if(end_cnt0)",
" cnt0 <= 0;",
" else",
" cnt0 <= cnt0 + 1;",
" end",
"end",
"",
"assign add_cnt0 = ;",
"assign end_cnt0 = add_cnt0 && cnt0== ;",
"",
"always_ff@(posedge clk or negedge rst_n)begin ",
" if(!rst_n)begin",
" cnt1 <= 0;",
" end",
" else if(add_cnt1)begin",
" if(end_cnt1)",
" cnt1 <= 0;",
" else",
" cnt1 <= cnt1 + 1;",
" end",
"end",
"",
"assign add_cnt1 = end_cnt0;",
"assign end_cnt1 = add_cnt1 && cnt1== ;",
"",
"always_ff@(posedge clk or negedge rst_n)begin",
" if(!rst_n)begin",
" cnt2 <= 0;",
" end",
" else if(add_cnt2)begin",
" if(end_cnt2)",
" cnt2 <= 0;",
" else",
" cnt2 <= cnt2 + 1;",
" end",
"end",
"",
"assign add_cnt2 = end_cnt1;",
"assign end_cnt2 = add_cnt2 && cnt2== ; ",
]
},
"TestPart template": {
"prefix": "TestPart",
"body": [
"//时钟周期，单位ns，在这里修改时钟周期",
"parameter CYCLE = 20;",
"",
"//复位时间，此时表示复位3个时钟周期的时间",
"parameter RST_TIME = 3;",
"",
"//生成本地时钟50M",
"initial begin",
" clk = 0;",
" forever",
" #(CYCLE/2)",
" clk=~clk;",
"end",
"",
"//产生复位信号",
"initial begin",
" rst_n = 1;",
" #2;",
" rst_n = 0;",
" #(CYCLE * RST_TIME);",
" rst_n = 1;",
"end",
"",
"//输入信号din0赋值方式",
"initial begin",
" #1;",
" //赋初值",
" din0 = 0;",
" #(10*CYCLE);",
" //开始赋值",
"",
"end",
"",
"//输入信号din1赋值方式",
"initial begin",
" #1;",
" //赋初值",
" din1 = 0;",
" #(10*CYCLE);",
" //开始赋值",
"",
"end",
"",
]
},
//模块接口
"inte":{
"prefix": "inte",
"body": [
"module ${TM_FILENAME_BASE}(",
"/********* system clock / reset *********/",
"input wire clk , //system clock",
"input wire rst_n , //reset signal",
"/********* ${var} *********/",
");",
"",
"endmodule",
""
]
},
//注释
"zhushi":{
"prefix": "zhushi",
"body": [
"//--------------------------- ${1} ---------------------------//",
"//function :${2}",
"//output :${3}",
"//describe :${4}",
""
]
},
//独热码状态机
"ohztj":{
"prefix": "ohztj",
"body": [
"`define STATE_W 4",
"`define STATE_B \\$clog2(`STATE_W)",
"",
"enum logic [`STATE_B-1:0]{",
" IDLE_BIT = 'd0 ,",
" S1_BIT = 'd1 ,",
" S2_BIT = 'd2 ,",
" S3_BIT = 'd3 ",
"}state_b;",
"",
"typedef enum logic [`STATE_W-1:0]{",
" IDLE = `STATE_W'd1 << IDLE_BIT ,",
" S1 = `STATE_W'd1 << S1_BIT ,",
" S2 = `STATE_W'd1 << S2_BIT ,",
" S3 = `STATE_W'd1 << S3_BIT ",
"}state_t;",
"",
"state state_c;",
"state state_n;",
"",
"always_ff@(posedge clk or negedge rst_n)begin",
" if(!rst_n)",
" state_c <= IDLE;",
" else",
" state_c <= state_n;",
"end",
"",
"always_comb begin",
" unique case (1)",
" state_c[IDLE_BIT]:begin",
" state_n = IDLE;",
" end",
" state_c[S1_BIT]:begin",
" state_n = S2;",
" end",
" state_c[S2_BIT]:begin",
" state_n = S3;",
" end",
" state_c[S3_BIT]:begin",
" state_n = IDLE;",
" end",
" default: begin",
" state_n = IDLE;",
" end",
" endcase",
"end"
]
}
}
VSCODE ——SystemVerilog模板
发布时间 2023-10-19 16:13:32作者: CNL中子