Flip-Flop Hardening and Selection for Soft Error and Delay Fault Resilience

https://ieeexplore.ieee.org/document/5372275
The traditional test model of go/no-go testing being questioned by increasing delay fault manifestations has become even further challenged as a result of unpredictable soft errors. Consequent probabilistic fault manifestations shift the focus to fault resilience mechanisms and tradeoffs of false alarms vs. escapes. Fault manifestation at flip-flops necessitates solutions that rely on their hardening, possibly imposing inordinate cost as flip-flops constitute a significant fraction of current designs. A two-pronged approach for resolving this challenge is necessitated, consisting of frugal flip-flop designs, capable of withstanding such faults, and an economic rationalization model to enable a prioritized flip-flop selection within an overall design budget. In this paper, we propose a hardened flip-flop that increases circuit tolerance to soft errors and delay faults simultaneously and the associated selective hardening scheme guided by a unified quality evaluation framework. The proposed flip-flop supersedes previous research efforts and simulation results show that the outlined framework delivers yield recovery and FIT reduction at a minimized hardware cost.
2023-03-20 19:28:32

1 Introduction

The continuous shrinking of VLSI devices and the fast increase in chip clock rates raise the challenging problem of ensuring that designs are meeting performance and reliability specifications. It has been widely observed that chips are increasingly susceptible to delay defects and soft errors, both more difficult to deal with using manufacturing test compared to traditional stuck-at faults. These potential reliability problems are becoming increasingly critical due to the aggressive technology scaling and design style. Additional test resources mitigate these problems only to a limited extent, while incurring a much larger testing cost, a quite unpalatable trade-off from a test economics point of view. The solution to these challenges necessitates the incorporation of reliability-oriented design techniques and economic models that guide their applications in product development.

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