1.参考例5.2.1，设计一个序列检测器。功能是检测出串行输入数据Sin中的4位二进制序列0101（自左至右输入），当检测到该序列时，输入Out=1；没有检测到该序列时，输入Out=0。要求不考虑序列重叠，如010101的序列中只包含一个0101序列。

module Detector2 (
input CP,Sin,nCR,
output reg Out
);

reg [1:0] Current_state,Next_state;
parameter S0=2'b00, S1=2'b01, S2=2'b10, S3=2'b11;
always @(posedge CP , negedge nCR)
begin
  if(~nCR) 
      begin
        Current_state = S0;
        Next_state = S0;
      end
      
  else
      Current_state = Next_state;
end
always @(Current_state, Sin)
begin
  Next_state=2'bxx;
  Out=1'b 0;
  case(Current_state)
    S0: begin Out=1'b0; Next_state=(Sin==1)? S0 : S1; end
    S1: begin Out=1'b0; Next_state=(Sin==1)? S2 : S1; end
    S2: begin Out=1'b0; Next_state=(Sin==1)? S0 : S3; end
    S3: if (Sin==1)
    begin Out=1'b1; Next_state=S0;  end
    else
    begin Out =1'b0; Next_state=S1; end
  endcase
end
endmodule

`timescale 1ms / 1ms
module Detector2test();
reg CP,Sin,nCR;
wire Out ;
  
// 实例化被测试模块
  Detector2 test (
    .Sin(Sin),
    .CP(CP),
    .nCR(nCR),
    .Out(Out)
  );   
initial 
  begin
    //Current_state=2'b00;
   // Next_state=2'b00;
    nCR=1'b0;
    CP=1'b0;
    #100 nCR = 1'b1;
    Sin=1'b0;
    #10Sin=1'b1;
    #10Sin=1'b0;
    #10Sin=1'b1;
    #10Sin=1'b0;
    #10Sin=1'b1;
    #10Sin=1'b0;
    #10Sin=1'b1;
    #10Sin=1'b0;
    #10Sin=1'b1;
    #10Sin=1'b0;
    #10Sin=1'b1;
    #10Sin=1'b0;
  end
always #5 CP = ~CP;
//always #10 Sin =~ Sin; 
  
   
  
   
 
 
endmodule