reduce pattern sim effort

发布时间 2023-07-27 17:18:16作者: zyy_note

1. invoke problem

  使用write_patterns保存pattern 做后续simulation时使用一些option来写出想要的格式, eg:

  -verilog  //pattern file 常用格式

  -parallel -pattern_set scan //verifies each scan register can reliably capture, 省略shift,仿真capture

  -serial -pattern_set chain // verifies all chains shift, 仿真shift,省略capture

  -serial -pattern_set scan // verifies all chains shift and capture,仿真shift和capture,run的时间最长

2. reduce tips:

  2.1 abort serial scan,run parallel scan + serial chain;

  2.2 sample patterns in the early-time;

  2.2 only run serial chain once for each fault type(stuck-at/transition)