SystemVerilog接口练习

 1 interface membus
 2 #(
 3     parameter LEN = 256, DW = 8
 4 )
 5 (
 6     input wire clk,
 7     input wire rst
 8 );
 9     logic [$clog2(LEN)-1:0] addr;
10     logic [DW-1:0] d, q;
11     logic wr;
12 
13     modport TEST(output addr, d, wr, input clk, rst, q);
14     modport DUT(input clk, rst, addr, d, wr, output q);
15 endinterface
16 
17 module mem
18 #(
19     parameter LEN = 256, DW = 8
20 )
21 (
22     membus.DUT bus
23 );
24     logic [DW-1:0] m[LEN]='{LEN{'0}};
25     always_ff @ (posedge bus.clk)                     
26     begin
27         if(bus.rst)
28             m <= '{LEN{'0}};
29         else if(bus.wr)
30             m[bus.addr] <= bus.d;
31     end
32 
33     always_ff @ (posedge bus.clk)
34     begin
35         if(bus.rst)
36             bus.q <= {DW{1'b0}};
37         else
38             bus.q <= m[bus.addr];
39     end
40 endmodule
41 
42 module mem_tester
43 #(
44     parameter LEN = 256, DW = 8
45 )
46 (
47     membus.TEST bus
48 );
49     initial 
50     begin
51         bus.addr = '0;
52     end
53 
54     always @ (posedge bus.clk)
55     begin
56         if(bus.rst)
57             bus.addr <= 0;
58         else
59             bus.addr <= bus.addr + 1'b1;
60     end
61 
62     assign bus.wr = 1'b1;
63     assign bus.d = bus.addr;
64 endmodule
65 
66 module Test;
67     logic clk = '0, rst = '0;
68 
69     always #5 clk = ~clk;
70 
71     initial
72     begin
73         #10 rst = '1;
74         #20 rst = '0;
75     end
76 
77     membus     #(64, 8) the_bus(clk, rst);
78     mem_tester #(64, 8) the_tester(the_bus);
79     mem        #(64, 8) the_mem(the_bus);
80 endmodule