disable_mmu_secure--关闭MMU，D Cache。
disable_mmu_icache_secure--关闭MMU，I/D Cache。

void sp_min_plat_arch_setup(void)
{
    const mmap_region_t bl_regions[] = {
        MAP_BL_SP_MIN_TOTAL,
        ARM_MAP_BL_RO,
#if USE_COHERENT_MEM
        ARM_MAP_BL_COHERENT_RAM,
#endif
        {0}
    };

    setup_page_tables(bl_regions, plat_arm_get_mmap());

    enable_mmu_svc_mon(0);
}

const mmap_region_t *plat_arm_get_mmap(void)
{
    return plat_arm_mmap;
}

const mmap_region_t plat_arm_mmap[] = {
    ARM_MAP_SHARED_RAM,
    V2M_MAP_IOFPGA,
    MAP_DEVICE0,
    {0}
};

void setup_mmu_cfg(uint64_t *params, unsigned int flags,
           const uint64_t *base_table, unsigned long long max_pa,
           uintptr_t max_va, __unused int xlat_regime)
{
    uint64_t mair, ttbr0;
    uint32_t ttbcr;

    /* Set attributes in the right indices of the MAIR */
    mair = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX);
    mair |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR,
            ATTR_IWBWA_OWBWA_NTR_INDEX);
    mair |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE,
            ATTR_NON_CACHEABLE_INDEX);--设置三组属性指代。

    /*
     * Configure the control register for stage 1 of the PL1&0 or EL2
     * translation regimes.
     */

    /* Use the Long-descriptor translation table format. */
    ttbcr = TTBCR_EAE_BIT;--使用40位页表转换。

    if (xlat_regime == EL1_EL0_REGIME) {
        assert(IS_IN_SVC() || IS_IN_MON());
        /*
         * Disable translation table walk for addresses that are
         * translated using TTBR1. Therefore, only TTBR0 is used.
         */
        ttbcr |= TTBCR_EPD1_BIT;--仅使用TTBR0的地址页表作为页表查询。不使用TTBR1。
    } else {
        assert(xlat_regime == EL2_REGIME);
        assert(IS_IN_HYP());

        /*
         * Set HTCR bits as well. Set HTTBR table properties
         * as Inner & outer WBWA & shareable.
         */
        ttbcr |= HTCR_RES1 |
             HTCR_SH0_INNER_SHAREABLE | HTCR_RGN0_OUTER_WBA |
             HTCR_RGN0_INNER_WBA;
    }

    /*
     * Limit the input address ranges and memory region sizes translated
     * using TTBR0 to the given virtual address space size, if smaller than
     * 32 bits.
     */
    if (max_va != UINT32_MAX) {
        uintptr_t virtual_addr_space_size = max_va + 1U;

        assert(virtual_addr_space_size >=
            xlat_get_min_virt_addr_space_size());
        assert(virtual_addr_space_size <=
            MAX_VIRT_ADDR_SPACE_SIZE);
        assert(IS_POWER_OF_TWO(virtual_addr_space_size));

        /*
         * __builtin_ctzll(0) is undefined but here we are guaranteed
         * that virtual_addr_space_size is in the range [1, UINT32_MAX].
         */
        int t0sz = 32 - __builtin_ctzll(virtual_addr_space_size);

        ttbcr |= (uint32_t) t0sz;
    }

    /*
     * Set the cacheability and shareability attributes for memory
     * associated with translation table walks using TTBR0.
     */
    if ((flags & XLAT_TABLE_NC) != 0U) {
        /* Inner & outer non-cacheable non-shareable. */
        ttbcr |= TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC |
            TTBCR_RGN0_INNER_NC;
    } else {
        /* Inner & outer WBWA & shareable. */
        ttbcr |= TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA |
            TTBCR_RGN0_INNER_WBA;
    }

    /* Set TTBR0 bits as well */
    ttbr0 = (uint64_t)(uintptr_t) base_table;--页表基地址，即tf_xlat_ctx.base_table。

    if (is_armv8_2_ttcnp_present()) {
        /* Enable CnP bit so as to share page tables with all PEs. */
        ttbr0 |= TTBR_CNP_BIT;
    }

    /* Now populate MMU configuration */
    params[MMU_CFG_MAIR] = mair;
    params[MMU_CFG_TCR] = (uint64_t) ttbcr;
    params[MMU_CFG_TTBR0] = ttbr0;
}

/* void enable_mmu_direct_svc_mon(unsigned int flags) */
func enable_mmu_direct_svc_mon
    /* Assert that MMU is turned off */
#if ENABLE_ASSERTIONS
    ldcopr  r1, SCTLR
    tst    r1, #SCTLR_M_BIT
    ASM_ASSERT(eq)
#endif

    /* Invalidate TLB entries */
    TLB_INVALIDATE(r0, TLBIALL)--根据flags决定是否置所有TLB无效。

    mov    r3, r0
    ldr    r0, =mmu_cfg_params--mmu_cfg_params存放MAIR/TTBCR/TTBR0寄存器的配置值，下面分别将r0指向的数据配置到寄存器中。

    /* MAIR0. Only the lower 32 bits are used. */
    ldr    r1, [r0, #(MMU_CFG_MAIR << 3)]
    stcopr    r1, MAIR0

    /* TTBCR. Only the lower 32 bits are used. */
    ldr    r2, [r0, #(MMU_CFG_TCR << 3)]
    stcopr    r2, TTBCR

    /* TTBR0 */
    ldr    r1, [r0, #(MMU_CFG_TTBR0 << 3)]
    ldr    r2, [r0, #((MMU_CFG_TTBR0 << 3) + 4)]
    stcopr16    r1, r2, TTBR0_64

    /* TTBR1 is unused right now; set it to 0. */
    mov    r1, #0
    mov    r2, #0
    stcopr16    r1, r2, TTBR1_64--TTBR1清零。

    /*
     * Ensure all translation table writes have drained into memory, the TLB
     * invalidation is complete, and translation register writes are
     * committed before enabling the MMU
     */
    dsb    ish
    isb

    /* Enable enable MMU by honoring flags */
    ldcopr  r1, SCTLR
    ldr    r2, =(SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT)--分别表示：可写属性强制被置为ExecuteNever；使能D Cache和Unified Cache；使能MMU。
    orr    r1, r1, r2

    /* Clear C bit if requested */
    tst    r3, #DISABLE_DCACHE
    bicne    r1, r1, #SCTLR_C_BIT

    stcopr    r1, SCTLR--配置MMU相关，此后MMU生效。
    isb

    bx    lr
endfunc enable_mmu_direct_svc_mon