Xilinx VIvado学习-01 数值处理之减法器

module un_sub(
input unsigned [7:0] a,
input unsigned [7:0] b,
output [7:0]  sub,
output carry
    );
 assign {carry,sub}=a-b;

endmodule

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/10/23 23:08:10
// Design Name: 
// Module Name: un_sub_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module un_sub_tb;
reg           sys_clk;
reg           unsigned [7:0] a;
reg           unsigned [7:0] b;
wire          signed [8:0] c;
wire   [7:0] sub;
wire   carry;
initial  sys_clk =1;
always #1 sys_clk = ~sys_clk;
//a = 8'h7f;
//b = 8'h2;

un_sub u_sub(
.a (a),
.b (b),
.sub (sub),
.carry(carry)
);
initial begin
a=0;b=0;
#2
a=49;b=73;

#2
a=116;b=108;
#2
a=61;b=108;
#2
a=63;b=125;
end
assign c = a-b;
  
endmodule