为什么要有p_sequencer?
sequence是从uvm_object拓展而来，所以不能访问uvm_component组成的uvm层次结构的，不能通过组件层次调用访问成员变量(如，在env中访问driver的成员变量htrans，可以通过m_env.m_agt.m_drv.htrans来访问)。那sequence如何访问uvm_component的成员变量呢？通过媒介：sequencer
怎么用？
UVM提供了强大的内建宏`uvm_declare_p_sequencer(SEQUENCER)来解决这个问题。呈上代码：
```verilog class case0_sequence extends uvm_sequence #(my_transaction); my_trasaction m_trans; `uvm_object_utils(case0_squence) `uvm_declare_p_sequencer(my_sequencer) //使用宏定义my_sequencer ... virtual task body(); ... repeat(10) begin `uvm_do_with(m_trans,{m_trans.dmac==p_sequencer.dmac; m_trans.smac==p_sequencer.smac;}) end ... endclass ```UVM通过`uvm_declare_p_sequencer宏将p_sequencer定义为my_sequencer,将m_sequencer通过$cast转换为q_sequencer类型（即my_sequencer类型）。
```verilog class case0_sequence extends uvm_sequence #(my_transaction); my_trasaction m_trans; `uvm_object_utils(case0_squence) ... virtual task body(); my_sequencer p_sequencer; ... $cast(p_sequencer,m_sequencer); ... repeat(10) begin `uvm_do_with(m_trans,{m_trans.dmac==p_sequencer.dmac; m_trans.smac==p_sequencer.smac;}) end ... endclass ```