proc_sys_reset 复位时序

module test(

    );
    
  bit slowest_sync_clk;
  bit ext_reset_in;
  bit aux_reset_in;
  bit mb_debug_sys_rst;
  bit mb_reset;

always #5 slowest_sync_clk = ~slowest_sync_clk;

initial begin
  ext_reset_in = 0;
  aux_reset_in = 0;
  mb_debug_sys_rst = 0;

  #100;
  ext_reset_in = 1;
  aux_reset_in = 1;
  mb_debug_sys_rst = 0;
  #800;
 aux_reset_in = 0; 
  #100;
aux_reset_in = 1; 

  #1500;
 mb_debug_sys_rst = 1; 
  #100;
mb_debug_sys_rst = 0; 
end
    proc_sys_reset_0 your_instance_name (
      .slowest_sync_clk(slowest_sync_clk),          // input wire slowest_sync_clk
      .ext_reset_in(ext_reset_in),                  // input wire ext_reset_in
      .aux_reset_in(aux_reset_in),                  // input wire aux_reset_in
      .mb_debug_sys_rst(mb_debug_sys_rst),          // input wire mb_debug_sys_rst
      .dcm_locked(1),                      // input wire dcm_locked
      .mb_reset(mb_reset),                          // output wire mb_reset
      .bus_struct_reset(),          // output wire [0 : 0] bus_struct_reset
      .peripheral_reset(),          // output wire [0 : 0] peripheral_reset
      .interconnect_aresetn(),  // output wire [0 : 0] interconnect_aresetn
      .peripheral_aresetn()      // output wire [0 : 0] peripheral_aresetn
    );
endmodule