1 module Conwaylife ( 2 input clk, 3 input load, 4 input [255:0] data, 5 output reg [255:0] q 6 ); 7 8 reg [3:0] w, r, c; 9 10 always @(posedge clk) begin 11 if (load) begin 12 q <= data; 13 end else begin 14 for (integer i = 0; i < $bits(q); i++) begin 15 r = i >> 4; // 注意不要使用阻塞赋值 16 c = i % 16; 17 18 w = q[16*((15+r)%16) + (15+c)%16 ] + 19 q[16*((15+r)%16) + c ] + 20 q[16*((15+r)%16) + (1+c)%16 ] + 21 q[16*r + (15+c)%16 ] + 22 q[16*r + (1+c)%16 ] + 23 q[16*((1+r)%16) + (15+c)%16 ] + 24 q[16*((1+r)%16) + c ] + 25 q[16*((1+r)%16) + (1+c)%16 ]; 26 27 if (w == 2) begin 28 q[i] <= q[i]; 29 end else if (w == 3) begin 30 q[i] <= 1; 31 end else begin 32 q[i] <= 0; 33 end 34 35 end 36 end 37 end 38 39 endmodule